GAURAV YADAV. Clock Gating Techniques for Power Optimization in PCIe TCP Header Generator Logic. International Journal of Scientific Research in Computer Science, Engineering and Information Technology, [S. l.], v. 11, n. 2, p. 2206–2218, 2025. DOI: 10.32628/CSEIT23112584. Disponível em: https://www.ijsrcseit.com/index.php/home/article/view/CSEIT23112584. Acesso em: 1 aug. 2025.